Techniques for an inductor at a first level interface

ABSTRACT

Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

PRIORITY APPLICATION

This application is a divisional of U.S. application Ser. No.16/012,259, filed Jun. 19, 2018, which is incorporated herein byreference in its entirety.

TECHNICAL FIELD

This document pertains generally, but not by way of limitation, toinductors, and more particularly, to an inductor formed at a first levelinterface of an integrated circuit.

BACKGROUND

Electronic circuit evolution continues to provide ever increasingfunctionality and speed from ever smaller systems. Such miniaturizationpressures circuit designers to use less components, in smaller sizes,yet deliver the same or improved performance. Inductors have also beenrelegated to the same design constraints. However, in certain terms,better inductor characteristics typically require increase size in atleast one dimension.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which are not necessarily drawn to scale, like numeralsmay describe similar components in different views. Like numerals havingdifferent letter suffixes may represent different instances of similarcomponents. Some embodiments are illustrated by way of example, and notlimitation, in the figures of the accompanying drawings in which:

FIGS. 1A-1C illustrate generally a perspective view of die packageincluding an inductor formed at a first level interface according tovarious examples of the present subject matter.

FIG. 2A illustrates generally top or bottom view of a first dieconfigured to form an inductor at a first level interface.

FIG. 2B illustrates generally top or bottom view of a second dieconfigured to form an inductor at a first level interface whenelectrically and mechanically coupled with the first die of FIG. 2A.

FIG. 3 illustrates generally a flowchart of an example method 300 formanufacturing an inductor at a first level interface that does notincrease the z-height of the stacked integrated circuit dies.

FIGS. 4A-4C illustrates generally an alternative configuration andmethod for an inductor 401 at a first level interface.

FIG. 5 illustrates a block diagram of an example machine upon which anyone or more of the techniques (e.g., methodologies) discussed herein mayperform. In alternative embodiments, the machine may operate as astandalone device or may be connected (e.g., networked) to othermachines.

FIG. 6 illustrates a system level diagram, depicting an example of anelectronic device (e.g., system) that can employ serial communicationimprovements as described in the present disclosure.

DETAILED DESCRIPTION

The following description and the drawings sufficiently illustratespecific embodiments to enable those skilled in the art to practicethem. Other embodiments may incorporate structural, logical, electrical,process, and other changes. Portions and features of some embodimentsmay be included in, or substituted for, those of other embodiments.Embodiments set forth in the claims encompass all available equivalentsof those claims.

The present inventors have recognized alternative techniques that canprovide an inductor with increased z-axis form factor yet not increasethe form factor of stacked integrated circuits connected at a firstlevel interface. As used herein, a first level interface is anelectrical and mechanical connection between a first semiconductor dieand a second semiconductor chip, such as an interposer, a second die ora substrate of a package. It is anticipated that future integratedcircuits may require significant power delivery improvements withoutincreasing in size, especially in vertical height which may be referredto as a z-axis dimension or z-height. Magnetic inductor arrays canprovide some improvement, but also require an external device that, inmost cases, add to or will not satisfy future z-height requirements.Enabling magnetic materials on a coreless substrate may satisfy bothfuture z-height requirements and performance, however, processes used toembed the magnetic components interact with wet chemistry processes suchas, but not limited to, desmear, eless Cu, flash etch, soft etch, orsurface finish. Magnetic materials can be exposed to the chemistry bathsduring processing and can result in premature corrosion, as well as,leaching of the magnetic materials into the baths. Such leaching cancorrupt the bath resulting in shorter bath life and diminished chemistryperformance, thus, adding additional costs to processing.

FIGS. 1A-1C illustrate generally a perspective view of die package 100including an inductor 101 formed at a first level interface according tovarious examples of the present subject matter. The die package 100 caninclude a first die 111, a second die 112, and interconnects 102 of thefirst level interface for electrically and mechanically connecting thefirst die 111 with the second die 112. Each of the first die 111 and thesecond die 112 can include traces 103 embedded within, or located on asurface, of a semiconductor substrate of the respective die 111, 112.Each trace 103 can form a portion of an inductor coil. Upon connectionof the first die 111 with the second die 112, the respective traces 103can from one or more coil loops of the inductor 101. In certainexamples, the inductor 101 does not include a magnetic core. In otherexamples, a magnetic material 107 can be applied to an external side ofthe substrate of either the first die 111, the second die 112, or acombination of the first die 111 and the second die 112 to provide amagnetic core inductor. FIG. 1A illustrates general a perspective viewof an example inductor 101 formed at a first level interface. FIG. 1Billustrate generally the example of FIG. 1A with dashed lines to showhidden features of the assembled first and second die 111, 112. FIG. 1Cillustrates generally the examples of FIGS. 1A and 1B with the solderballs interconnects 104 drawn as lines. FIG. 1C more clearly illustratesthe multiple coils formed when the first die 111 and the second die 112are electrically connected.

Each of the first die 111 and the second die 112 include traces 103 thatform the inductor 101 when the dies 111, 112 are electrically connectedtogether. The example of FIGS. 1A-1C show the traces 103 on or at asurface of each respective die 111, 112 that faces away from the centerof the inductor 103. Conductive through-silicon-vias (TSVs), orconductive vias 105 extending through the particular substrate materialof each die 111, 112, can couple a trace 103 to a respectiveinterconnect 104 or to an interconnect pad 106 used to electricallycouple the first and second dies 111, 112 together. In other examples,the traces 103 of each die can optionally be at or near the oppositesurface of the respective die 111, 112, for example, the surface of thedie facing the center of the inductor 101 and including the terminationfor the corresponding interconnect 104. In certain examples, such asthat shown in FIGS. 1A and 1B, the interconnects 104 between the firstdie 111 and the second die 112 can include solder balls. It isunderstood that other interconnects besides solder balls or bumps can beused without departing from the present subject matter, including, butnot limited to, connection pins, microballs (μballs), alloy paste, Cn/Snbumps, or other suitable interconnect structure for a first levelinterface.

FIG. 2A illustrates generally top or bottom view of a first die 211configured to form an inductor at a first level interface. The first die211 can include a substrate 220, and one or more traces 203 configuredto form a portion of each coil of the inductor. In some examples, thetraces 203 can be form on a surface of the first die 211. In someexamples, the traces 203 can be integrated with the semiconductorsubstrate 220 of the first die 211. In certain examples, the first die211 can optionally include vias 205, extending through the substrate220, to connect a trace embedded within the substrate 220, or on a firstsurface of the substrate 220, with a termination on a second surface ofthe substrate 220. In certain examples, two or more externalterminations of the first die 211 can connect with external terminationsof a second die 212. In certain examples, the first die 211 canoptionally include one or more terminations or one or more traces thatcouple the inductor to circuitry of the first die 211.

FIG. 2B illustrates generally top or bottom view of a second die 212configured to form an inductor at a first level interface whenelectrically and mechanically coupled with the first die 211 of FIG. 2A.The second die 212 can include a substrate 221, and one or more traces203 configured to form a portion of each coil of the inductor. In someexamples, the traces 203 can be located on a surface of the second die212. In some examples, the traces 203 can be integrated with thesemiconductor substrate 221 of the second die 212. In certain examples,the second die 212 can include vias 205 to connect a trace embeddedwithin the substrate 221, or on a first surface of the substrate 221,with a termination on a second surface of the substrate 221. In certainexamples, two or more external terminations of the second die 212 canconnect with external terminations of the first die 211 to form one ormore coils of the inductor. In certain examples, the second die 212 canoptionally include one or more terminations 215 or one or more tracesthat couple the inductor to circuitry of the second die.

In certain examples, the surface of one of the dies that faces theinside of the inductor coils can include a magnetic material such thatthe inductor includes a magnetic core. The magnetic material can beassembled to the surface the die after most, if not all, of the chemicalprocessing of the die has been completed. As such, the magnetic materialis not exposed to processing materials that can accelerate corrosion,and chemical baths used to process the die are not exposed tocontamination from the magnetic material.

FIG. 3 illustrates generally a flowchart of an example method 300 formanufacturing an inductor at a first level interface that does notincrease the z-height of the stacked integrated circuit dies. At 301, afirst portion of an inductor coil can be fabricated at or on a firstdie. In certain examples, the first portion can include a conductivetrace deposited on, grown on, or embedded within the substrate of thefirst die. In some examples, the first portion can include conductivevias to extend the trace to an external or internal termination of thefirst die.

At 303, a second portion of the inductor coil can be fabricated at or ona second die. In certain examples, the second portion can include aconductive trace deposited on, grown on, or embedded within thesubstrate of the second die. In some examples, the second portion caninclude conductive vias to extend the trace to an external or internaltermination of the second die.

At 305, the first die can be electrically and mechanically coupled withthe second die and can include electrically and mechanically couplingthe first portion of the inductor coil with the second portion of theinductor coil to provide an inductor having at least one conductive coilor turn. In certain examples, connecting the first portion of inductorcoil can be electrically connected with the second portion of theinductor coil using die-to-die interconnects such as solder balls orpins. In such cases, the die-to-die interconnects can become part of theinductor and can form a portion of an inductor coil.

In some examples, a core material of the inductor can be fabricated onat least one of the first die or the second die such that the corematerial traverses through a coil of the inductor formed by the firstportion, the second portion and the die-to-die interconnects. In someexamples, the core material can include a magnetic material, such as,but not limited to, a ferrous material, organic magnetic materials,inorganic magnetic materials, composite magnetic materials, orcombination thereof. In certain examples, the core material can beapplied using sputtering, spin coating, lamination, paste printing, orcombinations thereof.

FIGS. 4A-4C illustrates generally an alternative configuration andmethod for an inductor 401 at a first level interface. FIG. 4Aillustrates a first semiconductor die 411, a semiconductor interposer413, and a semiconductor substrate or second semiconductor die 412. Thefirst die 411 and the second die 412 can be fabricated to include traces403 for the inductor 401 using conventional semiconductor fabricationtechniques. Each individual trace 403 can form a portion of a coil ofthe inductor 401. FIG. 4B illustrates generally the assembled first die411 and interposer 413. Prior to assembly, a magnetic material 407 canbe applied to a surface of the first die 411, one or more surfaces ofthe interposer 413, or to a surface of the interposer 413 and a surfaceof the first die 411. The first die 411 and the interposer 413 can beassembled by, for example, thermal compression bonding (TCB), de-flux,and epoxy fill. Optionally, additional die 408 can be assembled to theinterposer 413 on the same side as the first die 411. In some examples,the inductor 401 can be completed upon assembly of the first die 411 andthe interposer 413 when the interposer 413 includes trace routings tocomplete the coils of the inductor 401.

FIG. 4C illustrates generally a package assembly 400 including theassembled first die 411 and interposer 413, and the second die 412. Incertain examples, traces or conductive vias 405 at the back side of theinterposer can be connected to the second die 412 using interconnects404 such as solder balls to complete the inductor 401. In such anexample, the interposer 413 includes traces and vias 405 to formvertical portions of inductor coils, and the first and second dies 411,412 include traces 403 to form horizon portions of the inductor coils.In some examples, magnetic material 407 can be applied to a surface ofthe second die 412. In general, the magnetic material 407 can be appliedto any or all of the first die 411, second die 412 or interposer 413such that upon assembly, the magnetic material 407 is enveloped withinthe coils of the inductor 401 as in the examples of FIGS. 1A-1C and2A-2B. In certain examples, the magnetic material 407 can be applied by,but not limited to, chemical vapor deposition or sputtering. Suchprocesses can allow use of insulating magnetic materials with higherpermeability (1400-2400) including, but not limited to, FeXN, where Feis iron, N is nitrogen and X can be Titanium (Ti), Aluminum (Al),Hafnium (Hf), Cobalt-Halfnium (CoHf), Chromium-Halfnium (CrHf).

FIG. 5 illustrates a block diagram of an example machine 500 upon whichany one or more of the techniques (e.g., methodologies) discussed hereinmay perform. In alternative embodiments, the machine 500 may operate asa standalone device or may be connected (e.g., networked) to othermachines. In a networked deployment, the machine 500 may operate in thecapacity of a server machine, a client machine, or both in server-clientnetwork environments. In an example, the machine 500 may act as a peermachine in peer-to-peer (or other distributed) network environment. Asused herein, peer-to-peer refers to a data link directly between twodevices (e.g., it is not a hub- and spoke topology). Accordingly,peer-to-peer networking is networking to a set of machines usingpeer-to-peer data links. The machine 500 may be a single-board computer,an integrated circuit package, a system-on-a-chip (SOC), a personalcomputer (PC), a tablet PC, a set-top box (STB), a personal digitalassistant (PDA), a mobile telephone, a web appliance, a network router,or other machine capable of executing instructions (sequential orotherwise) that specify actions to be taken by that machine. Further,while only a single machine is illustrated, the term “machine” shallalso be taken to include any collection of machines that individually orjointly execute a set (or multiple sets) of instructions to perform anyone or more of the methodologies discussed herein, such as cloudcomputing, software as a service (SaaS), other computer clusterconfigurations.

Examples, as described herein, may include, or may operate by, logic ora number of components, or mechanisms. Circuitry is a collection ofcircuits implemented in tangible entities that include hardware (e.g.,simple circuits, gates, logic, etc.). Circuitry membership may beflexible over time and underlying hardware variability. Circuitriesinclude members that may, alone or in combination, perform specifiedoperations when operating. In an example, hardware of the circuitry maybe immutably designed to carry out a specific operation (e.g.,hardwired). In an example, the hardware of the circuitry may includevariably connected physical components (e.g., execution units,transistors, simple circuits, etc.) including a computer readable mediumphysically modified (e.g., magnetically, electrically, moveableplacement of invariant massed particles, etc.) to encode instructions ofthe specific operation. In connecting the physical components, theunderlying electrical properties of a hardware constituent are changed,for example, from an insulator to a conductor or vice versa. Theinstructions enable embedded hardware (e.g., the execution units or aloading mechanism) to create members of the circuitry in hardware viathe variable connections to carry out portions of the specific operationwhen in operation. Accordingly, the computer readable medium iscommunicatively coupled to the other components of the circuitry whenthe device is operating. In an example, any of the physical componentsmay be used in more than one member of more than one circuitry. Forexample, under operation, execution units may be used in a first circuitof a first circuitry at one point in time and reused by a second circuitin the first circuitry, or by a third circuit in a second circuitry at adifferent time.

Machine (e.g., computer system) 500 may include a hardware processor 502(e.g., a central processing unit (CPU), a graphics processing unit(GPU), a hardware processor core, or any combination thereof), a mainmemory 504 and a static memory 506, some or all of which may communicatewith each other via an interlink (e.g., bus) 508. The machine 500 mayfurther include a display unit 510, an alphanumeric input device 512(e.g., a keyboard), and a user interface (UI) navigation device 514(e.g., a mouse). In an example, the display unit 510, input device 512and UI navigation device 514 may be a touch screen display. The machine500 may additionally include a storage device (e.g., drive unit) 516, asignal generation device 518 (e.g., a speaker), a network interfacedevice 520, and one or more sensors 521, such as a global positioningsystem (GPS) sensor, compass, accelerometer, or other sensor. Themachine 500 may include an output controller 528, such as a serial(e.g., universal serial bus (USB), parallel, or other wired or wireless(e.g., infrared (IR), near field communication (NFC), etc.) connectionto communicate or control one or more peripheral devices (e.g., aprinter, card reader, etc.). In certain examples, any one or more of thedisplay unit 510, storage device 516, network interface device orcombination thereof can include a multiple device PCIe card.

The storage device 516 may include a machine readable medium 522 onwhich is stored one or more sets of data structures or instructions 524(e.g., software) embodying or utilized by any one or more of thetechniques or functions described herein. The instructions 524 may alsoreside, completely or at least partially, within the main memory 504,within static memory 506, or within the hardware processor 502 duringexecution thereof by the machine 500. In an example, one or anycombination of the hardware processor 502, the main memory 504, thestatic memory 506, or the storage device 516 may constitute machinereadable media.

While the machine readable medium 522 is illustrated as a single medium,the term “machine readable medium” may include a single medium ormultiple media (e.g., a centralized or distributed database, and/orassociated caches and servers) configured to store the one or moreinstructions 524.

The term “machine readable medium” may include any medium that iscapable of storing, encoding, or carrying instructions for execution bythe machine 500 and that cause the machine 500 to perform any one ormore of the techniques of the present disclosure, or that is capable ofstoring, encoding or carrying data structures used by or associated withsuch instructions. Non-limiting machine readable medium examples mayinclude solid-state memories, and optical and magnetic media. In anexample, a massed machine readable medium comprises a machine readablemedium with a plurality of particles having invariant (e.g., rest) mass.Accordingly, massed machine-readable media are not transitorypropagating signals. Specific examples of massed machine readable mediamay include: non-volatile memory, such as semiconductor memory devices(e.g., Electrically Programmable Read-Only Memory (EPROM), ElectricallyErasable Programmable Read-Only Memory (EEPROM)) and flash memorydevices; magnetic disks, such as internal hard disks and removabledisks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

The instructions 524 may further be transmitted or received over acommunications network 526 using a transmission medium via the networkinterface device 520 utilizing any one of a number of transfer protocols(e.g., frame relay, internet protocol (IP), transmission controlprotocol (TCP), user datagram protocol (UDP), hypertext transferprotocol (HTTP), etc.). Example communication networks may include alocal area network (LAN), a wide area network (WAN), a packet datanetwork (e.g., the Internet), mobile telephone networks (e.g., cellularnetworks), Plain Old Telephone (POTS) networks, and wireless datanetworks (e.g., Institute of Electrical and Electronics Engineers (IEEE)802.11 family of standards known as Wi-Fi®, IEEE 802.16 family ofstandards known as WiMax®), IEEE 802.15.4 family of standards,peer-to-peer (P2P) networks, among others. In an example, the networkinterface device 520 may include one or more physical jacks (e.g.,Ethernet, coaxial, or phone jacks) or one or more antennas to connect tothe communications network 526. In an example, the network interfacedevice 520 may include a plurality of antennas to wirelessly communicateusing at least one of single-input multiple-output (SIMO),multiple-input multiple-output (MIMO), or multiple-input single-output(MISO) techniques. The term “transmission medium” shall be taken toinclude any intangible medium that is capable of storing, encoding orcarrying instructions for execution by the machine 500, and includesdigital or analog communications signals or other intangible medium tofacilitate communication of such software.

FIG. 6 illustrates a system level diagram, depicting an example of anelectronic device (e.g., system) including a PCIe card as described inthe present disclosure. FIG. 6 is included to show an example of ahigher level device application that can use serial interfaces, such asthose discussed above, exchange data between the illustrated components.In one embodiment, system 600 includes, but is not limited to, a desktopcomputer, a laptop computer, a netbook, a tablet, a notebook computer, apersonal digital assistant (PDA), a server, a workstation, a cellulartelephone, a mobile computing device, a smart phone, an Internetappliance or any other type of computing device. In some embodiments,system 600 is a system on a chip (SOC) system.

In one embodiment, processor 610 has one or more processor cores 612 and612N, where 612N represents the Nth processor core inside processor 610where N is a positive integer. In one embodiment, system 600 includesmultiple processors including 610 and 605, where processor 605 has logicsimilar or identical to the logic of processor 610. In some embodiments,processing core 612 includes, but is not limited to, pre-fetch logic tofetch instructions, decode logic to decode the instructions, executionlogic to execute instructions and the like. In some embodiments,processor 610 has a cache memory 616 to cache instructions and/or datafor system 600. Cache memory 616 may be organized into a hierarchalstructure including one or more levels of cache memory.

In some embodiments, processor 610 includes a memory controller 614,which is operable to perform functions that enable the processor 610 toaccess and communicate with memory 630 that includes a volatile memory632 and/or a non-volatile memory 634. In some embodiments, processor 610is coupled with memory 630 and chipset 620. Processor 610 may also becoupled to a wireless antenna 678 to communicate with any deviceconfigured to transmit and/or receive wireless signals. In oneembodiment, an interface for wireless antenna 678 operates in accordancewith, but is not limited to, the IEEE 602.11 standard and its relatedfamily, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, orany form of wireless communication protocol.

In some embodiments, volatile memory 632 includes, but is not limitedto, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic RandomAccess Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM),and/or any other type of random access memory device. Non-volatilememory 634 includes, but is not limited to, flash memory, phase changememory (PCM), read-only memory (ROM), electrically erasable programmableread-only memory (EEPROM), or any other type of non-volatile memorydevice.

Memory 630 stores information and instructions to be executed byprocessor 610. In one embodiment, memory 630 may also store temporaryvariables or other intermediate information while processor 610 isexecuting instructions. In the illustrated embodiment, chipset 620connects with processor 610 via Point-to-Point (PtP or P-P) interfaces617 and 622. Chipset 620 enables processor 610 to connect to otherelements in system 600. In some embodiments of the example system,interfaces 617 and 622 operate in accordance with a PtP communicationprotocol such as the Intel® QuickPath Interconnect (QPI) or the like. Inother embodiments, a different interconnect may be used.

In some embodiments, chipset 620 is operable to communicate withprocessor 610, 605N, display device 640, and other devices, including abus bridge 672, a smart TV 676, I/O devices 674, nonvolatile memory 660,a storage medium (such as one or more mass storage devices) 662, akeyboard/mouse 664, a network interface 666, and various forms ofconsumer electronics 677 (such as a PDA, smart phone, tablet etc.), etc.In one embodiment, chipset 620 couples with these devices through aninterface 624. Chipset 620 may also be coupled to a wireless antenna 678to communicate with any device configured to transmit and/or receivewireless signals.

Chipset 620 connects to display device 640 via interface 626. Display640 may be, for example, a liquid crystal display (LCD), a plasmadisplay, cathode ray tube (CRT) display, or any other form of visualdisplay device. In some embodiments of the example system, processor 610and chipset 620 are merged into a single SOC. In addition, chipset 620connects to one or more buses 650 and 655 that interconnect varioussystem elements, such as I/O devices 674, nonvolatile memory 660,storage medium 662, a keyboard/mouse 664, and network interface 666.Buses 650 and 655 may be interconnected together via a bus bridge 672.

In one embodiment, mass storage device 662 includes, but is not limitedto, a solid state drive, a hard disk drive, a universal serial bus flashmemory drive, or any other form of computer data storage medium. In oneembodiment, network interface 666 is implemented by any type ofwell-known network interface standard including, but not limited to, anEthernet interface, a universal serial bus (USB) interface, a PeripheralComponent Interconnect (PCI) Express interface, a wireless interfaceand/or any other suitable type of interface. In one embodiment, thewireless interface operates in accordance with, but is not limited to,the IEEE 602.11 standard and its related family, Home Plug AV (HPAV),Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wirelesscommunication protocol.

While the modules shown in FIG. 6 are depicted as separate blocks withinthe system 600, the functions performed by some of these blocks may beintegrated within a single semiconductor circuit or may be implementedusing two or more separate integrated circuits. For example, althoughcache memory 616 is depicted as a separate block within processor 610,cache memory 616 (or selected aspects of 616) can be incorporated intoprocessor core 612.

Additional Notes

In a first example, Example 1, an apparatus can include a first diehaving first plurality of external terminations, a second die having asecond plurality of external terminations, a plurality of connectorscoupling the first plurality of external terminations to the secondplurality of external terminations, and an inductor winding comprisingthe plurality of connectors.

In Example 2, an integrated circuit package optionally includes thesecond die of Example 1.

In Example 3, the plurality of connectors of any one or more of Examples1-2 optionally includes solder balls.

In Example 4, the apparatus of any one or more of Examples 1-3optionally includes a magnetic material disposed within the inductorwinding and disposed between the first die and the second die.

In Example 5, the plurality of connectors of any one or more of Examples1-4 optionally is arranged in two groups and the magnetic material isdisposed between the two groups of connectors.

In Example 6, the magnetic material of any one or more of Examples 1-5optionally is mechanically coupled to a surface of the first die, thesurface directly adjacent the second die.

In Example 7, the magnetic material of any one or more of Examples 1-6optionally is mechanically coupled to a surface of the second die, thesurface directly adjacent the first die.

In Example 8, an inductor can include a winding, and a core disposedinside the winding. The winding can include first conductive traces of afirst die, second conductive traces of a second die, a plurality ofconnectors configured to connect the first die with the second die, andeach connector of the plurality of connecters can be located between atrace of the first conductive traces and a corresponding trace of thesecond conductive traces.

In Example 9, an integrated circuit package optionally includes thesecond die of any one or more of Examples 1-8 optionally.

In Example 10, the plurality of connectors of any one or more ofExamples 1-9 optionally includes solder balls.

In Example 11, the core of any one or more of Examples 1-10 optionallyincludes a magnetic material within the winding and located between thefirst die and the second die.

In Example 12, the plurality of connectors of any one or more ofExamples 1-11 optionally is arranged in two groups and the magneticmaterial is disposed between the two groups of connectors.

In Example 13, the magnetic material of any one or more of Examples 1-12optionally is mechanically coupled to a surface of the first die, thesurface directly adjacent the second die.

In Example 14, the magnetic material of any one or more of Examples 1-13optionally is mechanically coupled to a surface of the second die, thesurface directly adjacent the first die.

In Example 15, a method can include fabricating a first portion of aninductor coil at a substrate of a first die, fabrication a secondportion of the inductor coil at a substrate of a second die, andelectrically and mechanically coupling the first die and the firstportion of the inductor coil with the second die and the second portionof the inductor coil.

In Example 16, the fabricating the first portion of the inductor coil ofany one or more of Examples 1-15 optionally includes coupling a trace ofthe substrate forming a first portion of a first winding coil to firstand second external terminations of the second die, the trace configuredto form a first portion of a first complete winding of the inductorcoil.

In Example 17, the method of any one or more of Examples 1-16 optionallyincludes depositing a magnetic material to the substrate of the firstdie between the first and second external terminations of the first die.

In Example 18, the fabricating the second portion of the inductor coilof any one or more of Examples 1-17 optionally includes coupling a traceof the second die to first and second external terminations of thesecond die.

In Example 19, the method of any one or more of Examples 1-18 optionallyincludes depositing a magnetic material to a surface of the second diebetween the first and second external terminations of the second die.

In Example 20, the electrically and mechanically coupling the first dieand first portion of inductor coil with the second die and secondportion of inductor coil of any one or more of Examples 1-19 optionallyincludes mechanically and electrically coupling a trace of the firstportion of the inductor coil with a trace of the second portion of theinductor coil using a solder ball connector.

The above detailed description includes references to the accompanyingdrawings, which form a part of the detailed description. The drawingsshow, by way of illustration, specific embodiments in which theinvention can be practiced. These embodiments are also referred toherein as “examples.” Such examples can include elements in addition tothose shown or described. However, the present inventors alsocontemplate examples in which only those elements shown or described areprovided. Moreover, the present inventors also contemplate examplesusing any combination or permutation of those elements shown ordescribed (or one or more aspects thereof), either with respect to aparticular example (or one or more aspects thereof), or with respect toother examples (or one or more aspects thereof) shown or describedherein.

In this document, the terms “a” or “an” are used, as is common in patentdocuments, to include one or more than one, independent of any otherinstances or usages of “at least one” or “one or more.” In thisdocument, the term “or” is used to refer to a nonexclusive or, such that“A or B” includes “A but not B,” “B but not A,” and “A and B,” unlessotherwise indicated. In this document, the terms “including” and “inwhich” are used as the plain-English equivalents of the respective terms“comprising” and “wherein.” Also, in the following claims, the terms“including” and “comprising” are open-ended, that is, a system, device,article, composition, formulation, or process that includes elements inaddition to those listed after such a term in a claim are still deemedto fall within the scope of that claim. Moreover, in the followingclaims, the terms “first,” “second,” and “third,” etc. are used merelyas labels, and are not intended to impose numerical requirements ontheir objects.

The above description is intended to be illustrative, and notrestrictive. For example, the above-described examples (or one or moreaspects thereof) may be used in combination with each other. Otherembodiments can be used, such as by one of ordinary skill in the artupon reviewing the above description. The Abstract is provided to complywith 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain thenature of the technical disclosure. It is submitted with theunderstanding that it will not be used to interpret or limit the scopeor meaning of the claims. Also, in the above Detailed Description,various features may be grouped together to streamline the disclosure.This should not be interpreted as intending that an unclaimed disclosedfeature is essential to any claim. Rather, inventive subject matter maylie in less than all features of a particular disclosed embodiment.Thus, the following claims are hereby incorporated into the DetailedDescription, with each claim standing on its own as a separateembodiment, and it is contemplated that such embodiments can be combinedwith each other in various combinations or permutations. The scope ofthe invention should be determined with reference to the appendedclaims, along with the full scope of equivalents to which such claimsare legally entitled.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor die having a plurality of external terminations; asubstrate coupled to the semiconductor die with a number of solderinterconnects; an inductor winding comprising at least some of theplurality of external terminations, the number of solder interconnects,and a plurality of traces in the substrate; and a layer of magneticmaterial disposed in a space between the semiconductor die and thesubstrate, the layer of magnetic material located within the number ofsolder interconnects between the semiconductor die and the substrate. 2.The semiconductor device of claim 1, wherein the layer of magneticmaterial is attached to the semiconductor die.
 3. The semiconductordevice of claim 1, wherein the layer of magnetic material is attached tothe substrate.
 4. The semiconductor device of claim 1, wherein thenumber of solder interconnects includes a number of solder balls.
 5. Thesemiconductor device of claim 1, wherein the number of solderinterconnects are arranged in two parallel rows.
 6. The semiconductordevice of claim 1, wherein the traces in the substrate are on a surfaceof the substrate adjacent to the semiconductor die.
 7. The semiconductordevice of claim 1, wherein the traces in the substrate are on a surfaceof the substrate facing away from the semiconductor die.
 8. Thesemiconductor device of claim 1, wherein the magnetic material includesan insulating magnetic material.
 9. The semiconductor device of claim 1,wherein the magnetic material includes an FeXN, where X includes one ormore metal element.
 10. A semiconductor device, comprising: asemiconductor die having a plurality of external terminations; aninterposer coupled to the semiconductor die with a first number ofsolder interconnects; a substrate coupled to the interposer with asecond number of solder interconnects; an inductor winding comprising atleast some of the plurality of external terminations, the number offirst solder interconnects, the number of second solder interconnects,and a plurality of traces in the substrate; and a layer of magneticmaterial disposed in a space between the semiconductor die and theinterposer, the layer of magnetic material located within the number offirst number of solder interconnects between the semiconductor die andthe interposer.
 11. The semiconductor device of claim 10, wherein theinterposer includes a silicon interposer.
 12. The semiconductor deviceof claim 10, further including a second layer of magnetic materialdisposed in a space between the interposer and the substrate, the secondlayer of magnetic material located within the number of second number ofsolder interconnects between the interposer and the substrate.
 13. Thesemiconductor device of claim 10, wherein the layer of magnetic materialincludes an insulating magnetic material.
 14. The semiconductor deviceof claim 10, wherein the layer of magnetic material includes an FeXN,where X includes one or more metal element.
 15. The semiconductor deviceof claim 12, wherein the second layer of magnetic material includes aninsulating magnetic material.
 16. The semiconductor device of claim 12,wherein the second layer of magnetic material includes an FeXN, where Xincludes one or more metal element.